SX1240, Rev 1, Oct 2010

©2010 Semtech Corp.

SX1240

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Page 10

Integrated Transmitter IC

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

3.2. Application Mode: Advanced

3.2.1. Advanced Mode: Configuration

Advanced mode can be accessed as described on Figure 3. Programming is performed via a two wire interface (TWI)

formed by CTRL and DATA pins.

Programming of the configuration register is triggered by a rising edge on the CTRL line. Upon detection of this rising edge,

the data applied to the DATA pin is accepted as register configuration information, the data bits are clocked on subsequent

rising edges of the clocking signal applied to the CTRL pin. The first bit of serial data selects register read or write operation

(Read = ‘high’ and Write = ‘low’). The timing for SX1240 configuration register ‘write’ is shown in Figure 5. Note that, once

triggered, all 13 data bits must be written to the SX1240.

The contents of the configuration register and the role of each bit therein is described in Table 8 of Section 4.

Figure 5. TWI Configuration Register ‘Write’.

Similarly, the configuration register may be read using the timing of Figure 6.

Figure 6. TWI Configuration Register ‘Read’.

Notes - Logic level ‘0’ on DATA during the first rising edge on CTRL is required to start the TWI access

- Reading only the 13 configuration bits D0 to D12 is not allowed on the SX1240. In Read access, 64 clock cycles

on CTRL pin must be issued, shifting out on pin DATA the 13 configuration bits (D0 to D12), plus 43 internal test

bits (T0 to T42). Read access should be used when developing the device firmware, but is not intended for use in

the normal operation mode.

- During the register ‘write’ or ‘read’ phases the SX1240 remains in sleep mode.

DATA

D12

D11

D10

D9

D7

D8

D6

D5

D4

D3

D1

D0

D2

‘0’

‘0’

ACC

R/W

CTRL

‘0’

CTRL

DATA

‘0’

‘0’

‘0’

‘0’

‘0’

D12

D11

D10

D1

D0

‘1’

‘0’

ACC

R/W

T42

T41

T1

T0

‘0’

DATA pin is an output