CYWUSB6953_10 datasheet(30/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 30 of 68

15.2.4 LPOSC Trim

15.3 CPU Clock During Sleep Mode

When the CPU enters sleep mode, the oscillator is stopped. When the CPU comes out of sleep mode it is running on the internal

oscillator. The internal oscillator recovery time is three clock cycles of the Internal 32 kHz Low power Oscillator.

Table 15-6. LPOSC Trim (LPOSCTR) [0x36] [R/W]

Bit #

Field

32 kHz Low

Power

Reserved

32 kHz Bias Trim [1:0]

32 kHz Freq Trim [3:0]

Read/Write

R/W

–

R/W

Default

–

This register is used to calibrate the 32 kHz Low speed Oscillator. The reset value is undefined but during boot the SROM writes

a calibration value that is determined during manufacturing test. This is the meaning of ‘D’ in the Default field. The trim value can

be adjusted vs. voltage as noted in Table 15-2 on page 26.

Bit 7

32 kHz Low Power

0 = The 32 kHz Low speed Oscillator operates in normal mode.

1 = The 32 kHz Low speed Oscillator operates in a low power mode. The oscillator continues to function normally

but with reduced accuracy.

Bit 6

Reserved

Bits [5:4]

32 kHz Bias Trim [1:0]

These bits control the bias current of the low power oscillator.

0 0 = Mid bias

0 1 = High bias

1 0 = Reserved

1 1 = Reserved

Important Note Do not program the 32 kHz Bias Trim [1:0] field with the reserved 10b value as the oscillator does not oscillate

at all corner conditions with this setting.

Bits 3:0

32 kHz Freq Trim [3:0]

These bits are used to trim the frequency of the low power oscillator.

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