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PIC16F1847 Datasheet(PDF) 39 Page - Microchip Technology |
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PIC16F1847 Datasheet(HTML) 39 Page - Microchip Technology |
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39 / 408 page  2011 Microchip Technology Inc. Preliminary DS41453B-page 39 PIC16(L)F1847 Bank 31 F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 F83h(1) STATUS — — —TO PD ZDC C ---1 1000 ---q quuu F84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu F85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 F86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu F87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 F88h(1) BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 F89h(1) WREG Working Register 0000 0000 uuuu uuuu F8Ah(1) PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 F8Bh(1) INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000u F8Ch — FE3h — Unimplemented — — FE4h STATUS_ SHAD — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu FE5h WREG_ SHAD Working Register Shadow 0000 0000 uuuu uuuu FE6h BSR_ SHAD — — — Bank Select Register Shadow ---x xxxx ---u uuuu FE7h PCLATH_ SHAD — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu FE8h FSR0L_ SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu FE9h FSR0H_ SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu FEAh FSR1L_ SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_ SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu FECh — Unimplemented — — FEDh STKPTR — — — Current Stack pointer ---1 1111 ---1 1111 FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuu FEFh TOSH — Top-of-Stack High byte -xxx xxxx -uuu uuuu TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. |
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