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PIC16F1847 Datasheet(PDF) 97 Page - Microchip Technology |
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PIC16F1847 Datasheet(HTML) 97 Page - Microchip Technology |
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97 / 408 page  2011 Microchip Technology Inc. Preliminary DS41453B-page 97 PIC16(L)F1847 8.5.9 PIR4 REGISTER The PIR4 register contains the interrupt flag bits, as shown in Register 8-9. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Note 1: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 — — — — — — BCL2IF SSP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware bit 7-2 Unimplemented: Read as ‘0’ bit 1 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A Bus Collision was detected (must be cleared in software) 0 = No Bus collision was detected bit 0 SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit 1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software) 0 = Waiting to Transmit/Receive/Bus Condition in progress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 89 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 177 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 90 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE 91 PIE3 — — CCP4IE CCP3IE TMR6IE —TMR4IE — 92 PIE4 — — — — — — BCL2IE SSP2IE 93 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 94 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — — CCP2IF 95 PIR3 — — CCP4IF CCP3IF TMR6IF —TMR4IF — 96 PIR4 — — — — — — BCL2IF SSP2IF 97 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. |
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