PIC16F1847 datasheet(91/408 Pages) MICROCHIP

91 / 408 page

 2011 Microchip Technology Inc.

Preliminary

DS41453B-page 91

PIC16(L)F1847

8.5.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 8-3.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0

U-0

R/W-0/0

OSFIE

C2IE

C1IE

EEIE

BCL1IE

—

CCP2IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

OSFIE:

Oscillator Fail Interrupt Enable bit

= Enables the Oscillator Fail interrupt

= Disables the Oscillator Fail interrupt

bit 6

C2IE:

Comparator C2 Interrupt Enable bit

= Enables the Comparator C2 interrupt

= Disables the Comparator C2 interrupt

bit 5

C1IE:

Comparator C1 Interrupt Enable bit

= Enables the Comparator C1 interrupt

= Disables the Comparator C1 interrupt

bit 4

EEIE:

EEPROM Write Completion Interrupt Enable bit

= Enables the EEPROM Write Completion interrupt

= Disables the EEPROM Write Completion interrupt

bit 3

BCL1IE:

MSSP1 Bus Collision Interrupt Enable bit

= Enables the MSSP1 Bus Collision Interrupt

= Disables the MSSP1 Bus Collision Interrupt

bit 2-1

Unimplemented:

Read as ‘0’

bit 0

CCP2IE:

CCP2 Interrupt Enable bit

= Enables the CCP2 interrupt

= Disables the CCP2 interrupt

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