PIC32MX795F512LT-80ISLASHPF datasheet(103/256 Pages) MICROCHIP

103 / 256 page

TABLE 4-38:

PARALLEL MASTER PORT REGISTER MAP(1)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

7000

PMCON

31:16

—

0000

15:0

FRZ

SIDL

ADRMUX<1:0>

PMPTTL

PTWREN

PTRDEN

CSF<1:0>

ALP

CS2P

CS1P

—

WRSP

RDSP

0000

7010 PMMODE

31:16

—

0000

15:0

BUSY

IRQM<1:0>

INCM<1:0>

MODE16

MODE<1:0>

WAITB<1:0>

WAITM<3:0>

WAITE<1:0>

0000

7020 PMADDR

31:16

—

0000

15:0 CS2EN/A15 CS1EN/A14

ADDR<13:0>

0000

7030 PMDOUT

31:16

DATAOUT<31:0>

0000

15:0

0000

7040

PMDIN

31:16

DATAIN<31:0>

0000

15:0

0000

7050

PMAEN

31:16

—

0000

15:0

PTEN<15:0>

0000

7060

PMSTAT

31:16

—

0000

15:0

IBF

IBOV

—

IB3F

IB2F

IB1F

IB0F

OBE

OBUF

—

OB3E

OB2E

OB1E

OB0E

008F

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more

information.

TABLE 4-39:

PROGRAMMING AND DIAGNOSTICS REGISTER MAP

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

F200 DDPCON

31:16

—

0000

15:0

—

—JTAGEN

TROEN

—TDOEN

0008

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

PIC32MX795F512LT-80I/PF Datasheet(PDF) 103 Page - Microchip Technology

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