IMX53CEC datasheet(6/204 Pages) FREESCALE

6 / 204 page

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Introduction

•

On-chip LDO voltage regulators for PLLs

Security functions are enabled and accelerated by the following hardware:

•

ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so

on)

•

Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking

the access to the system debug features

•

Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and

mechanism to detect voltage and clock glitches

•

Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine

•

SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator

(TRNG)

•

Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure

RAM and support for multiple keys as well as TZ/non-TZ separation

•

Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is

configured during boot by e-fuses, and determines the security level operation mode as well as the

TrustZone (TZ) policy

•

Advanced High Assurance Boot (A-HAB)—HAB with the following embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization

NOTE

The actual feature set depends on the part number as described in Table 1.

Functions such as video hardware acceleration with 2D and 3D hardware

graphics acceleration may not be enabled for specific part numbers.

IMX53CEC Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc