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IMX53CEC Datasheet(PDF) 135 Page - Freescale Semiconductor, Inc |
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IMX53CEC Datasheet(HTML) 135 Page - Freescale Semiconductor, Inc |
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135 / 204 page ![]() Electrical Characteristics i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 135 Figure 87. UART IrDA Mode Transmit Timing Diagram 4.7.17.3.4 UART IrDA Mode Receiver Figure 88 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 91 lists the receive timing characteristics. Figure 88. UART IrDA Mode Receive Timing Diagram Table 90. IrDA Mode Transmit Timing Parameters ID Parameter Symbol Min Max Units UA3 Transmit Bit Time in IrDA mode tTIRbit 1/Fbaud_rate 1 – Tref_clk 2 1 F baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 T ref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). 1/Fbaud_rate + Tref_clk — UA4 Transmit IR Pulse Duration tTIRpulse (3/16)*(1/Fbaud_rate) – Tref_clk (3/16)*(1/Fbaud_rate)+ Tref_clk — Table 91. IrDA Mode Receive Timing Parameters ID Parameter Symbol Min Max Units UA5 Receive Bit Time1 in IrDA mode 1 The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/(16*Fbaud_rate). tRIRbit 1/Fbaud_rate 2 – 1/(16*Fbaud_rate) 2 F baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 1/Fbaud_rate + 1/(16*Fbaud_rate) — UA6 Receive IR Pulse Duration tRIRpulse 1.41 us (5/16)*(1/Fbaud_rate)— Bit 1 Bit 2 Bit 0 Bit 4 Bit 5 Bit 6 Bit 7 TXD (output) Bit 3 Start Bit STOP BIT Possible Parity Bit UA3 UA3 UA3 UA3 UA4 Bit 1 Bit 2 Bit 0 Bit 4 Bit 5 Bit 6 Bit 7 RXD (input) Bit 3 Start Bit STOP BIT Possible Parity Bit UA5 UA5 UA5 UA5 UA6 |
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