PCA9663 datasheet(39/66 Pages) NXP

39 / 66 page

PCA9663

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Product data sheet

Rev. 1 — 6 June 2011

39 of 66

NXP Semiconductors

PCA9663

Parallel bus to 3 channel Fm+ I2C-bus controller

8.2 Read transactions

Many I2C-bus slave devices need a command or register offset to setup a read operation.

In this case, a read transaction is actually a multi-part transaction consisting of a write

transaction followed by a read transaction. This is done by setting the transactions in that

order when programming the sequence.

If no write is required prior to a read, then the read transaction can be placed in any

location of the sequence. Once the read transaction is completed (i.e., the TR bit is

cleared to 0) the data is immediately available for the host to retrieve it on the parallel bus.

8.3 Stopping a sequence

If the host needs to stop the execution of a sequence, it should set the STO bit in the

CONTROL register. For write transactions, the host will issue a STOP after the

acknowledge cycle of the current byte being transferred on the serial bus. For read

transactions, if the host sets the STO bit while an address + read bit (SLA+R) is sent, the

controller will complete the read of one byte by sending 9 clocks and a NACK on the ninth

clock before sending the STOP condition. If the host sets the STO bit while a read

transaction is in progress, the current byte will be NACKed before sending a STOP

condition. No interrupts will be generated and all the status registers will be up to date.

The Sequence Done bit (SD) will be set to indicate to the host that the STOP condition

was completed and the bus is idle. The Sequence Done and the Frame Loop Done will be

set if the channel is in Loop mode (FRAMECNT

 1) and a STO or STOSEQ bit is set.

If the host issues a STOP (by setting the STO) in the middle of a sequence followed by a

START (by setting the STA), then the controller will re-send the sequence from the

beginning, not from the point where the sequence was last stopped.

8.4 Looping a sequence

A sequence can be set to automatically loop several times using the FRAMECNT and one

of the following:

• The REFRATE register. The REFRATE register contains the value of the refresh rate

which is timing required between the START of two sequences. The refresh rate is

derived from the internal clock of the bus controller. If the REFRATE is programmed to

00h, the sequences will be looped back-to-back.

• Trigger enable (TE) bit. When TE is set, the refresh rate is controlled by the external

trigger input and the contents of the REFRATE registers is ignored. There is no

maximum timing requirement for the trigger interval.

The FRAMECNT register sets the number of times the sequence will be repeated. A

frame is defined as a sequence associated with its respective refresh rate. As described

above, the frame refresh rate is determined by the REFRATE register or an external

trigger source.

During looping, there is no host intervention required and all status and error reporting

remains active. The SD (Sequence Done) bit can be masked to avoid getting interrupted

each time a frame is completed while the other error reporting bits remain unmasked. In

this manner, normal transactions can run without host intervention and errors will be

reported at the STOP of the current byte where the error occurred.

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