PCA9663 datasheet(13/66 Pages) NXP

13 / 66 page

PCA9663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 6 June 2011

13 of 66

NXP Semiconductors

PCA9663

Parallel bus to 3 channel Fm+ I2C-bus controller

7.5.1 Channel registers

7.5.1.1

STATUS0_[n], STATUS1_[n], STATUS2_[n] — Transaction status registers

STATUS0_[n], STATUS1_[n], and STATUS2_[n] are 8-bit

 64 read-only registers that

provide status information for a given transaction. Only the 5 lower bits are used; the

top bits will always read 0. When some of these bits are set, a channel interrupt is

requested (the INT pin is asserted LOW). A read to STATUSx_[n] register will clear its

status. To clear all the STATUSx_[n] registers, a byte-by-byte read of all STATUSx_[n]

registers is required. The controller will auto-clear the STATUSx_[n] registers at each

START of a sequence when FRAMECNT = 1 and only at the first START when

FRAMECNT

 1.

Each register byte can be accessed by direct addressing so that the host can choose to

read the status on one or more individual transactions without having to read all

64 status bytes.

Remark: When STATUSx_[n] = 00h, no interrupt is requested and the transaction is in the

Done/Idle state.

During program execution, the TR and TA bits behave as follows:

Example, we are to transfer 3 transactions in a sequence. All initialization is completed

(loading of SLA, TRANCONFIG, DATA) and device is ready for serial transfer.

Before the STA bit is set, the STATUSx_[n] register will contain:

STATUSx_[0] = 0

STATUSx_[1] = 0

STATUSx_[2] = 0

STATUSx_[3] = 0

Table 4.

STATUSx_[n] - Transaction status code register bit description

Bit

Symbol Description

7:5

ST[7:5]

always reads 000

RSN

Read slave NACK. When HIGH, a NACK was received after a slave address was

transmitted on the serial bus on a read transaction. An interrupt will be requested.

WSN

Write slave NACK. When HIGH, a NACK was received after a slave address was

transmitted on the serial bus on a write transaction. An interrupt will be requested.

WDN

Write data NACK. When HIGH, a NACK was received for a data byte during a

write transaction on the serial bus. An interrupt will be requested.

Transaction active. When 1, the transaction is currently active on the serial bus.

No interrupt is requested.

Transaction ready. When 1, a transaction is loaded in the buffer and waiting to be

executed. No interrupt is requested.

PCA9663 Datasheet(PDF) 13 Page - NXP Semiconductors

PCA9663 Datasheet(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL