LH28F016SC-L datasheet(21/44 Pages) SHARP

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LH28F016SC-L/SCH-L

- 21 -

Set Lock-Bit

Complete

Start

Write 60H,

Block/Device Address

Write 01H/F1H,

Block/Device Address

Read

Status Register

SR.7 =

Full Status

Check if Desired

Repeat for subsequent lock-bit set operations.

Full status check can be done after each lock-bit set

operation or after a sequence of lock-bit set operations.

Write FFH after the last lock-bit set operation to place device

in read array mode.

BUS

OPERATION

Write

Read

Standby

COMMAND

Set

Block/Master

Lock-Bit

Setup

COMMENTS

Data = 60H

Addr = Block Address (Block),

Device Address (Master)

Data = 01H (Block),

F1H (Master)

Addr = Block Address (Block),

Device Address (Master)

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

SR.3 =

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

VPP Range Error

SR.1 =

Device Protect Error

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SR.1

1 = Device Protect Detect

RP# = VIH

(Set Master Lock-Bit Operation)

RP# = VIH, Master Lock-Bit is Set

(Set Block Lock-Bit Operation)

Check SR.4

1 = Set Lock-Bit Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear

Status Register command in cases where multiple lock-bits are

set before full status is checked.

If error is detected, clear the status register before attempting

retry or other error recovery.

Set

Block or Master

Lock-Bit

Confirm

Set Lock-Bit

Successful

SR.4, 5 =

Command Sequence

Error

SR.4 =

Set Lock-Bit

Error

Standby

Check SR.3

1 = VPP Error Detect

Standby

Check SR.4, 5

Both 1 = Command Sequence Error

Fig. 7

Set Block and Master Lock-Bit Flowchart

LH28F016SC-L Datasheet(PDF) 21 Page - Sharp Corporation

LH28F016SC-L Datasheet(HTML) 21 Page - Sharp Corporation

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