LH28F016SC-L datasheet(29/44 Pages) SHARP

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LH28F016SC-L/SCH-L

- 29 -

6.2.3 DC CHARACTERISTICS (contd.)

SYMBOL

PARAMETER

NOTE

VCC = 2.7 to 3.6 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V

UNIT

TEST

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

CONDITIONS

VIL

Input Low Voltage

–0.5

0.8

–0.5

0.8

–0.5

0.8

VIH

Input High Voltage

2.0

VCC

2.0

VCC

2.0

VCC

+0.5

VCC = VCC Min.

VOL

Output Low Voltage

3, 7

0.4

0.45

IOL = 5.8 mA (5 V)

IOL = 2.0 mA (3.3 V, 2.7 V)

Output High Voltage

VCC = VCC Min.

VOH1

(TTL)

3, 7

2.4

IOH = –2.5 mA (5 V)

IOH = –2.0 mA (3.3 V, 2.7 V)

0.85

VCC = VCC Min.

VOH2

Output High Voltage

3, 7

VCC

IOH = –2.5 mA

(CMOS)

VCC

VCC = VCC Min.

–0.4

IOH = –100 µA

VPPLK

VPP Lockout Voltage during

4, 7

1.5

Normal Operations

VPP Voltage during

VPPH1 Byte Write, Block Erase

—

3.0

3.6

—

or Lock-Bit Operations

VPP Voltage during

VPPH2 Byte Write, Block Erase

—

4.5

5.5

4.5

5.5

or Lock-Bit Operations

VPP Voltage during

VPPH3 Byte Write, Block Erase

—

11.4

12.6

11.4

12.6

or Lock-Bit Operations

VLKO

VCC Lockout Voltage

2.0

Set master lock-bit

VHH

RP# Unlock Voltage

8, 9

—

11.4

12.6

11.4

12.6

Override master and

block lock-bit

NOTES :

All currents are in RMS unless otherwise noted. Typical

values at nominal VCC voltage and TA = +25˚C. These

currents are valid for all product versions (packages and

speeds).

ICCWS and ICCES are specified with the device de-

selected. If reading or byte writing in erase suspend

mode, the device’s current draw is the sum of ICCWS or

ICCES and ICCR or ICCW, respectively.

Includes RY/BY#.

Block erases, byte writes, and lock-bit configurations are

inhibited when VPP

≤ VPPLK, and not guaranteed in the

range between VPPLK (max.) and VPPH1 (min.), between

VPPH1 (max.) and VPPH2 (min.), between VPPH2 (max.)

and VPPH3 (min.), and above VPPH3 (max.).

Automatic Power Saving (APS) reduces typical ICCR to

1 mA at 5 V VCC and 3 mA at 2.7 V and 3.3 V VCC in

static operation.

CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL

inputs are either VIL or VIH.

Sampled, not 100% tested.

Master lock-bit set operations are inhibited when RP# =

VIH. Block lock-bit configuration operations are inhibited

when the master lock-bit is set and RP# = VIH. Block

erases and byte writes are inhibited when the

corresponding block lock-bit is set and RP# = VIH. Block

erase, byte write, and lock-bit configuration operations

are not guaranteed with VCC < 3.0 V or VIH < RP# <

VHH and should not be attempted.

RP# connection to a VHH supply is allowed for a

maximum cumulative period of 80 hours.

LH28F016SC-L Datasheet(PDF) 29 Page - Sharp Corporation

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