LH28F016SC-L datasheet(39/44 Pages) SHARP

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LH28F016SC-L/SCH-L

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6.2.7 RESET OPERATIONS

VIH

VOH

VOL

VIL

RY/BY# (R)

(A) Reset During Read Array Mode

(B) Reset During Block Erase, Byte Write, or Lock-Bit Configuration

tPLPH

RP# (P)

VIH

VOH

VOL

VIL

RY/BY# (R)

tPLRH

tPLPH

RP# (P)

VIH

2.7 V/3.3 V/5 V

VIL

VCC

t235VPH

RP# (P)

Fig. 16

AC Waveform for Reset Operation

Reset AC Specifications (NOTE 1)

NOTES :

These specifications are valid for all product versions

(packages and speeds).

If RP# is asserted while a block erase, byte write, or

lock-bit configuration operation is not executing, the reset

will complete within 100 ns.

A reset time, tPHQV, is required from the latter of RY/BY#

or RP# going high until outputs are valid.

When the device power-up, holding RP#-low minimum

100 ns is required after VCC has been in predefined

range and also has been in stable there.

VCC = 2.7 to 3.6 V

VCC = 3.3±0.3 V

VCC = 5.0±0.5 V

SYMBOL

PARAMETER

NOTE

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

UNIT

RP# Pulse Low Time

tPLPH

(If RP# is tied to VCC, this

100

specification is not applicable)

RP# Low to Reset during

tPLRH

Block Erase, Byte Write or

2, 3

—

µs

Lock-Bit Configuration

VCC 2.7 V to RP# High

t235VPH

VCC 3.0 V to RP# High

100

VCC 4.5 V to RP# High

LH28F016SC-L Datasheet(PDF) 39 Page - Sharp Corporation

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