SIP11203 datasheet(7/18 Pages) VISHAY

7 / 18 page

Document Number: 73868

S11-0975–Rev. C, 16-May-11

www.vishay.com

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

MOSFET RECTIFIER DRIVERS

Start-Up

At converter start-up, VL will typically be at or near 0 V.

Until such time as the UVLOR threshold is exceeded,

the main synchronous rectifier drivers are disabled, as

the supply voltage for the IC may be insufficient to

ensure that the output drivers will fully respond to input

commands.

Without

precautionary

measures,

capacitive coupling between the drains and gates of

the synchronous rectifiers could cause spurious

conduction in the rectifiers. To prevent this, special

hold-off MOSFETs are switched in until the main

drivers

are

enabled.

These

internal

hold-off

MOSFETs, which connect from OUTA to PGND and

OUTB to PGND, can typically conduct in excess of

400 mA with 1 V on OUTA or OUTB (ZOUT 2.5 ).

Once VL rises above UVLOR, the main drivers are

enabled and the part assumes its normal mode of

operation, with pulses at INA being used to control

OUTA and pulses at INB being used to control OUTB.

Figure 3 and its related text provide additional details

on this topic.

Normal Operation

When enabled, the main driver outputs are non-

inverting with respect to the input signal. The drivers

are designed to provide the high peak currents

(2 - 4 A) required to rapidly charge and discharge the

gates of large synchronous rectifier MOSFETs, with a

greater turn-off (pull-down) current than turn-on

(pull-up) current, to prevent shoot-through in the

synchronous rectifiers.

Shut-Down

In the typical application circuit, cessation of primary

timing signals at INA and INB would cause both OUTA

and OUTB to be pulled high, which at the system level

would short-circuit of the converter output to ground

via the synchronous rectifiers. To avoid possible

negative effects of such an event, the SiP11203/

SiP11204 uses a missing-pulses detector to monitor

INA and INB and, if necessary, set the main output

drivers to a high-impedance state. At the same time

that the main drivers are disabled, a pull-down device

(current sink) of user-settable value is enabled on each

output, to gradually discharge OUTA and OUTB,

thereby performing a soft turn-off of the rectifier

MOSFETs. The pull-down current is set by the RPD

resistor,

and

given

the

formula

IPULL-DOWN = 500 V/RPD. Such an event also causes

bypass capacitor at the the VREF pin to be discharged,

preparing the IC for a voltage-loop soft-start should the

primary resume sending timing signals. Further details

are given in the Applications Information section.

Synchronous Rectifier Phase-In

With a resistor connected between the RDEL pin and

ground, the SiP11203/SiP11204 will increase the low-

to-high propagation delay time from INA and INB to

OUTA and OUTB by an amount

T

DEL. This interval

is proportional to the resistance used, and inversely

proportional to the voltage on VREF (TDEL = k x RDEL/

VREF). As this delay occurs for high-going input

transitions only, it constitutes a hold-off time for the

synchronous rectifiers. As can be seen,

T

DEL

decreases as VREF ramps from a low level to its final

1.225 V level at start-up, or following any soft-start

event. If

T

DEL is set to start at a sufficient value to

allow only diode-mode conduction in the rectifier

MOSFETs, the result will be a gentle transition from

diode-mode

operation

fully

synchronous

rectification, thereby avoiding a sudden change in the

average voltage drop seen at the output rectifiers.

Conventional operation can be achieved by tying the

RDEL pin to VL. The synchronous rectifier phase-in

function is explained in more detail in the Applications

Information section.

Output Over-voltage Protection: SiP11203 versus

SiP11204

For maximum flexibility in the way that the SiP11203/

SiP11204 parts react to an output over-voltage event,

the input to the over-voltage protect comparator

(OVPIN) is brought out separately from the error

amplifier inputs. Additionally, the outputs of the

SiP11203 and the SiP11204 respond differently to

an over-voltage: the SiP11203 is designed to rapidly

discharge an output bus that is experiencing an over-

voltage, while the SiP11204 is designed to avoid

sinking current from other supplies feeding the same

bus, relying instead upon system-level intervention to

provide complete load protection. The OVPIN function

is explained in more detail in the Applications

Information section.

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