SIP11203 datasheet(8/18 Pages) VISHAY

8 / 18 page

www.vishay.com

Document Number: 73868

S11-0975–Rev. C, 16-May-11

Vishay Siliconix

SiP11203, SiP11204

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

APPLICATIONS INFORMATION

Powering SiP11203/SiP11204

The SiP11203/SiP11204 has an internal pre-regulator

to provide 5 V at VL, which biases many of the internal

sub-circuits. This allows the IC to operate from any

input voltage within the allowable VIN range. At the

same time, VIN provides the supply voltage to the gate

driver outputs (OUTA and OUTB) directly. The gate

drive level to the synchronous rectifier MOSFETs is

determined by VIN

The VIN voltage can be derived using conventional

methods, such as an extra winding on the power

transformer or on the output inductor. Alternatively,

this supply can be derived from the pulse transformer

used to transmit synchronous rectifier timing signals

from the primary to the secondary, as shown in Figure

2 below. The voltage level on VIN will be determined by

the turn ratio of the pulse transformer and the

differential voltage between SRL of the Si9122,

Si9122A, Si9122E and SRH of of the Si9122, Si9122A,

Si9122E. Note that this circuit will cause the voltages

at INA and INB to be twice that of VIN. Therefore it may

be necessary to limit the voltage seen by INA and INB

in order to avoid exceeding their recommended

operating values.

START-UP DRIVER OPERATION

During

start-up

the

SiP11203/SiP11204,

the

MOSFET drivers (OUTA and OUTB) are disabled until

VL is at 90 % of its final value. To fully prevent any

spurious

turn-on

the

synchronous

rectifier

MOSFETs, the gates of the MOSFETs are held off

during this start up period. Until the main drivers are

enabled, the INA and INB drive paths are re-routed, or

“swapped,” inside the IC. In conjunction with a

dedicated n-channel hold-off MOSFET “inverter”

placed in parallel with each main driver, this allows the

IC to ground the appropriate synchronous rectifier gate

at the necessary time. See Figure 3.

If the first two pulses coming through the pulse

transformer are considered, the following sequence of

events follows:

• INA goes low, which would normally command the

OUTA driver to go low. This would prevent spurious

turn-on of the associated synchronous rectifier.

However, since the voltage to the IC is below its

normal operating level, it cannot be guaranteed that

OUTA can in fact go to its necessary state. For this

reason, the OUTA and OUTB drivers are disabled

while VL < UVLOR.

• When INA goes low, INB will be driven to a level of

2 x VIN. This is due to the way in which the

secondary of the pulse transformer is rectified to

provide VIN. Specifically, this results from the

rectifier diodes clamping the secondary’s negative

excursions one diode drop below ground (See

Figure 2).

Figure 2. Typical schematic showing how the VIN supply for SiP11203/SiP11204 is generated using the pulse transformer providing the

synchronous rectifier timing signals

SRH

SRL

INA

INB

GND

SiP11203

SiP11204

SRH

SRL

INA

INB

GND

SiP11203

SiP11204

SiP11203

SiP11204

SIP11203 Datasheet(PDF) 8 Page - Vishay Siliconix

SIP11203 Datasheet(HTML) 8 Page - Vishay Siliconix

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL