CDCUN1208LP datasheet(34/43 Pages) TI

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STOP

START

STOP

tBUS

tSU(START)

SDA

SCL

th(START)

tr(SM)

tSU(SDATA)

tW(SCLL)

tW(SCLH)

th(SDATA)

tr(SM)

tf(SM)

tSU(STOP)

VIH(SM)

VIL(SM)

VIH(SM)

VIL(SM)

ACK

CDCUN1208LP

SCAS928 – MAY 2012

www.ti.com

I2C Timing

Figure 40 and Table 13 provide details regarding the timing requirements for I2C:

Figure 40. I2C Timing Diagram

Table 13. I2C Timing Requirements

SYMBOL

PARAMETER

MIN

MAX

UNITS

fSCL

SCL Clock Frequency

100

kHz

tsu(START)

START Setup Time (SCL high before SDA low)

4.7

µs

th(START)

START Hold Time (SCL low after SDA low)

4.0

µs

tw(SCLL)

SCL Low-pulse duration

4.7

µs

tw(SCLH)

SCL High-pulse duration

4.0

µs

th(SDA)

SDA Hold Time (SDA valid after SCL low)

3.45

µs

tsu(SDA)

SDA Setup Time

250

SCL / SDA input rise time

1000

SCL / SDA input fall time

300

tsu(STOP)

STOP Setup Time

4.0

µs

tBUS

Bus free time between a STOP and START condition

4.7

µs

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