Analog Integrated Circuit Device Data



Freescale Semiconductor

29

33814

5.1.31 VRS Deglitching Filters

The VRS input circuit has additional filters on the rising and falling edges of the input waveforms to reduce the effect of short

transitions that may occur during those noise sensitive times. The deglitching filters are approximately 1% of the last positive

pulse period. The deglitch filters are enabled by setting the deglitch bit (bit 3) in the SPI VRS miscellaneous parameters

configuration register. This bit is, by default, zero (0), meaning that the deglitch filters are disabled.

5.1.32 High/Low Reference Bit

The High/Low reference bit in the SPI VRS miscellaneous configuration register is used to change the use of the input high pulse

timing to input low pulse timing, in cases where an elongated tooth wheel is being used rather than the missing tooth wheel. The

default for this bit is zero (0), indicating the use of a crankshaft wheel with a missing tooth (or teeth).

5.1.33 Disable VRS bit

The disable VRS bit in the SPI VRS miscellaneous configuration register is used to disable the VRS input circuitry when there is

no need for a VRS input conditioning circuit. This would be the case, for example, if the crankshaft wheel sensor was a hall effect

device whose output could be directly input to the MCU. The default for this bit is zero (0) indicating that the VRS input

conditioning circuitry is active.

5.1.34 Clamp Active Status bits

There are two clamp active status bits in the SPI VRS status register. One is for the low pulse clamp and the other is for the high

pulse clamp. When either of these bits are a one (1), it indicates that the peak voltage for that part of the input waveform has

exceeded the clamp voltage and is being clamped to the high or low voltage limit. These status bits can be used to indicate that

the engine has attained the speed necessary to switch from “cranking” values for the threshold and blanking (in the SPI VRS

control register) to the “running” values. (in the SPI VRS configuration register).

5.1.35 Pre-driver Operation

There are three identical pre-drivers in the 33814. Each pre-driver can be configured as either an ignition (IGBT) pre-driver or a

general purpose gate driver (GPGD). By default, one pre-driver is configured as a GPGD (O2HOUT) and two pre-drivers are

configured as ignition (IGNOUT1, IGNOUT2) pre-drivers.

A bit in each of the SPI Configuration registers, for each pre-driver, defines whether the pre-driver behaves as an ignition or a

GPGD pre-driver.

It should be noted that there are only two current measurement circuits, ISGNSENSP/N and O2SENSP/N. When all three pre-

drivers are used as GPGD, then IGNSENSP/N is associated with the IGNOUT1 pre-driver only, and the O2SENSP/N is

associated with the O2OUT pre-driver. The IGNOUT2 pre-driver will not have an associated current sense circuit and will rely on

Short to Battery (drain voltage sense) protection only. When all three pre-drivers are used as ignition predrivers, then IGNOUT1

and IGNOUT2 will share the IGNSENSP/N current measurement circuit, and IGNOUT3 (O2HOUT) will have its own current

sense circuit, O2SENSP/N.

5.1.36 O2HIN Input

The O2HIN pin is the parallel input that controls the O2HOUT pre-driver output. The O2HIN pin is a 5.0 V logic level input with

a built-in pull-down to ground to prevent accidental actuation of the pre-driver output if the connection to the pin is lost. As a

default, the O2HIN input is ORed with the O2HOUT control bit in the SPI ON/OFF control word. This is to allow the O2HOUT to

be controlled by either the O2HIN (parallel input) or via the SPI.