STA381BWS datasheet(58/171 Pages) STMICROELECTRONICS

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STA381BWS

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Doc ID 018937 Rev 6

Note:

(*): Clock is BICKI

6.13.2

Interpolation ratio selection

The STA381BWS has variable interpolation (oversampling) settings such that internal

processing and FFX output rates remain consistent. The first processing block interpolates

by either 3 times (Table 83: PLL register 0x56 bits D0), 2 times or 1 time (pass-through) or

provides a 2-times downsample. The oversampling ratio of this interpolation is determined

by the IR bits.

6.13.3

Fault-detect recovery bypass

Table 28.

Input sampling rates

Input

sampling rate

fs (kHz)

MCS[2:0]

111

110

101

100

011

010

001

000

32, 44.1, 48

64*fs(*)

576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs

88.2, 96

64*fs(*) 32*fs(*)

64 * fs

128 * fs 192 * fs 256 * fs 384 * fs

176.4, 192

64*fs(*) 32*fs(*)

32 * fs

64 * fs

96 * fs

128 * fs 192 * fs

Table 29.

Internal interpolation ratio

Bit

R/W

RST

Name

Description

4:3

R/W

IR [1:0]

Selects internal interpolation ratio based on input I2S

sampling frequency

Table 30.

IR bit settings as a function of the input sampling rate

Input sampling rate fs (kHz)

1st stage interpolation ratio

2-times oversampling

44.1

2-times oversampling

88.2

Pass-through

176.4

2-times downsampling

192

2-times downsampling

Table 31.

Fault-detect recovery bypass

Bit

R/W

RST

Name

Description

7R/W

FDRB

0: fault-detect recovery enabled

1: fault-detect recovery disabled

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