SPC560B64L5 datasheet(105/134 Pages) STMICROELECTRONICS

105 / 134 page

SPC560B54/6x

Electrical characteristics

Doc ID 15131 Rev 6

105/134

CP1

CC D

ADC_0 input pin

capacitance 1

——

—

CP2

CC D

ADC_0 input pin

capacitance 2

——

—

CP3

CC D

ADC_0 input pin

capacitance 3

——

—

RSW1

CC D

Internal resistance of

analog source

——

—

RSW2

CC D

Internal resistance of

analog source

——

—

RAD

CC D

Internal resistance of

analog source

——

—

IINJ

SR — Input current Injection

Current

injection on

one ADC_0

input,

different

from the

converted

one

VDD =

3.3 V ± 10%

−5—

VDD =

5.0 V ± 10%

−5—

| INL |

Absolute integral

nonlinearity

No overload

—

0.5

1.5

LSB

| DNL |

Absolute differential

nonlinearity

No overload

—

0.5

1.0

LSB

| EO |

T Absolute offset error

—

0.5

—

LSB

| EG |

T Absolute gain error

—

0.6

—

LSB

TUEP

P Total unadjusted error(7)

for precise channels, input

only pins

Without current injection

−20.6

LSB

With current injection

−3—

TUEX

T Total unadjusted error(7)

for extended channel

Without current injection

−31

LSB

With current injection

−44

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified.

Analog and digital VSS must be common (to be tied together externally).

VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0x3FF.

Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal

divider by 2.

During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the end of

the sampling time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values for the

sampling clock tADC0_S depend on programming.

This parameter does not include the sampling time tADC0_S, but only the time for determining the digital result and the time

to load the result’s register with the conversion result.

Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

Table 45.

ADC_0 conversion characteristics (10-bit ADC_0) (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

SPC560B64L5 Datasheet(PDF) 105 Page - STMicroelectronics

SPC560B64L5 Datasheet(HTML) 105 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL