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SPC560D40L1 Datasheet(PDF) 59 Page - STMicroelectronics

Part # SPC560D40L1
Description  32-bit MCU family built on the Power Architecture® for automotive body electronics applications
PDF  82 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPC560D40L1 Datasheet(HTML) 59 Page - STMicroelectronics

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SPC560D30x, SPC560D40x
Electrical characteristics
Doc ID 16315 Rev 5
59/82
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin;
furthermore, it sources charge during the sampling phase, when the analog signal source is
a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: CS being substantially a switched capacitance, with a frequency
equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For
instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of
330 k
Ω is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the
considered channel). To minimize the error induced by the voltage partitioning between this
resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external
circuit must be designed to respect the Equation 4:
Equation 4:
Equation 4 generates a constraint for external network design, in particular on a resistive
path. Internal switch resistances (RSW and RAD) can be neglected with respect to external
resistances.
V
A
R
S
R
F
R
L
R
SW
R
AD
++
+
+
R
EQ
---------------------------------------------------------------------------
•
1
2
---LSB
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