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SPC560D40L1 Datasheet(PDF) 63 Page - STMicroelectronics |
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SPC560D40L1 Datasheet(HTML) 63 Page - STMicroelectronics |
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63 / 82 page ![]() SPC560D30x, SPC560D40x Electrical characteristics Doc ID 16315 Rev 5 63/82 charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS: Equation 11: From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Equation 12: 4.17.3 ADC electrical characteristics V A2 V A ------------ C P1 C P2 +C F + C P1 C P2 +C F C S ++ -------------------------------------------------------- = C F 2048 C S • > Table 41. ADC input leakage current Symbol C Parameter Conditions Value Unit Min Typ Max ILKG CC C Input leakage current TA = −40 °C No current injection on adjacent pin —1— nA CTA =25 °C — 1 — CTA = 105 °C — 8 200 PTA = 125 °C — 45 400 Table 42. ADC conversion characteristics Symbol C Parameter Conditions(1) Value Unit Min Typ Max VSS_ADC SR — Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) (2) — −0.1 — 0.1 V VDD_ADC SR — Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) —VDD − 0.1 — VDD +0.1 V VAINx SR — Analog input voltage(3) —VSS_ADC − 0.1 — VDD_ADC +0.1 V fADC SR — ADC analog frequency VDD =5.0 V 3.33 — 32 + 4% MHz VDD =3.3 V 3.33 — 20 + 4% |
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