SPC560D40L1 datasheet(64/82 Pages) STMICROELECTRONICS

64 / 82 page

Electrical characteristics

SPC560D30x, SPC560D40x

64/82

Doc ID 16315 Rev 5

ΔADC_SYS SR —

ADC clock duty cycle

(ipg_clk)

ADCLKSEL = 1(4)

—55

tADC_PU SR — ADC power up delay

—

——

1.5

µs

Sampling time(5)

VDD = 3.3 V

fADC = 20 MHz,

INPSAMP = 12

600

—

fADC = 3.33 MHz,

INPSAMP = 255

—

76.2

µs

Sampling time(5)

VDD = 5.0 V

fADC = 24 MHz,

INPSAMP = 13

500

—

fADC = 3.33 MHz,

INPSAMP = 255

—

76.2

µs

Conversion time(6)

VDD = 3.3 V

fADC = 20 MHz,

INPCMP = 0

2.4

—

µs

fADC = 13.33 MHz,

INPCMP = 0

——

3.6

Conversion time(6)

VDD = 5.0 V

fADC = 32 MHz,

INPCMP = 0

1.5

—

µs

fADC = 13.33 MHz,

INPCMP = 0

——

3.6

CC D

ADC input sampling

capacitance

—

CP1

CC D

ADC input pin

capacitance 1

—

CP2

CC D

ADC input pin

capacitance 2

—

CP3

CC D

ADC input pin

capacitance 3

—

1.5

RSW1

CC D

Internal resistance of

analog source

——

—

RSW2

CC D

Internal resistance of

analog source

——

—

RAD

CC D

Internal resistance of

analog source

——

—

0.3

IINJ

SR — Input current Injection

Current

injection on

one ADC input,

different from

the converted

one

VDD =

3.3 V ± 10%

−5—

VDD =

5.0 V ± 10%

−5

—

INLP

CC T

Absolute Integral non-

linearity-precise

channels

No overload

—1

LSB

Table 42.

ADC conversion characteristics (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

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