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SPC564L54L5 Datasheet(PDF) 8 Page - STMicroelectronics |
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SPC564L54L5 Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 160 page ![]() Introduction SPC56XL60/54 8/160 Doc ID 15457 Rev 8 Table 1. SPC56XL60/54 device summary Feature SPC56EL60 SPC56EL54 CPU Type 2 × e200z4 (in lock-step or decoupled operation) 2 × e200z4 (in lock-step or decoupled operation) Architecture Harvard Harvard Execution speed 0–120 MHz (+2% FM) 0–120 MHz (+2% FM) DMIPS intrinsic performance >240 MIPS >240 MIPS SIMD (DSP + FPU) Yes Yes MMU 16 entry 16 entry Instruction set PPC Yes Yes Instruction set VLE Yes Yes Instruction cache 4 KB, EDC 4 KB, EDC MPU-16 regions Yes, replicated module Yes, replicated module Semaphore unit (SEMA4) Yes Yes Buses Core bus AHB, 32-bit address, 64-bit data AHB, 32-bit address, 64-bit data Internal periphery bus 32-bit address, 32-bit data 32-bit address, 32-bit data Crossbar Master × slave ports Lock Step Mode: 4 × 3 Decoupled Parallel Mode: 6 × 3 Lock Step Mode: 4 × 3 Decoupled Parallel Mode: 6 × 3 Memory Flash 1 MB, ECC, RWW 768 K, ECC, RWW Static RAM (SRAM) 128 KB, ECC 96 KB, ECC |
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