SPC564L54L5 datasheet(99/160 Pages) STMICROELECTRONICS

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SPC56XL60/54

Electrical characteristics

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3.4

Thermal characteristics

VDD_HV_ADV

SR 3.3 V ADC supply voltage

—

3.0

3.6

VSS_HV_AD0

VSS_HV_AD1

ADC_0 ground and low reference voltage

ADC_1 ground and low reference voltage

—0

VSS_HV_ADV

SR 3.3 V ADC supply ground

—

VDD_LV_REGCOR

(3)

SR Internal supply voltage

—

VSS_LV_REGCOR

(4)

SR Internal reference voltage

—

VDD_LV_CORx

(2)

SR Internal supply voltage

—

VSS_LV_CORx

(3)

SR Internal reference voltage

—

VDD_LV_PLL

(2)

SR Internal supply voltage

—

VSS_LV_PLL

(3)

SR Internal reference voltage

—

SR Ambient temperature under bias

fCPU ≤ 120 MHz

–40

125

°C

SR Junction temperature under bias

—

–40

150

°C

Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and

I/Os DC electrical specification may not be guaranteed.

VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same voltage

source.

Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced by an

on-chip voltage regulator.

For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds

(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one is used.

Table 10.

Recommended operating conditions (3.3 V) (continued)

Symbol

Parameter

Conditions

Min(1)

Max

Unit

Table 11.

Thermal characteristics for LQFP100 package(1)

Symbol

Parameter

Conditions

Value

Unit

RθJA

Thermal resistance, junction-to-ambient natural

convection(2)

Single layer board – 1s

°C/W

Four layer board – 2s2p

RθJMA

Thermal resistance, junction-to-ambient forced

convection at 200 ft/min

Single layer board – 1s

°C/W

Four layer board – 2s2p

RθJB

Thermal resistance junction-to-board(3)

—19

°C/W

RθJC

Thermal resistance junction-to-case(4)

—8

°C/W

ΨJT

Junction-to-package-top natural convection(5)

—2

°C/W

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification

for the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

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