SPC564L54L5 datasheet(14/160 Pages) STMICROELECTRONICS

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Introduction

SPC56XL60/54

14/160

Doc ID 15457 Rev 8

The eDMA module provides the following features:

●

16 channels supporting 8-, 16-, and 32-bit value single or block transfers

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Support variable sized queues and circular buffered queue

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Source and destination address registers independently configured to post-increment

or stay constant

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Support major and minor loop offset

●

Support minor and major loop done signals

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DMA task initiated either by hardware requestor or by software

●

Each DMA task can optionally generate an interrupt at completion and retirement of the

task

●

Signal to indicate closure of last minor loop

●

Transfer control descriptors mapped inside the SRAM

The eDMA controller is replicated for each processing channel.

1.5.5

On-chip flash memory with ECC

This device includes programmable, non-volatile flash memory. The non-volatile memory

(NVM) can be used for instruction storage or data storage, or both. The flash memory

module interfaces with the system bus through a dedicated flash memory array controller. It

supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to

flash memory. The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow

no-wait responses. Buffer misses incur a 3 wait state response at 120 MHz.

The flash memory module provides the following features

●

Up to 1 MB of flash memory in unique multi-partitioned hard macro

●

Sectorization:

–

1 MB: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB

–

768 KB: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 1 × 256 KB

●

EEPROM emulation (in software) within same module but on different partition

●

16 KB test sector and 16 KB shadow block for test, censorship device and user option

bits

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Wait states:

–

3 wait states for frequencies =< 120 MHz

–

2 wait states for frequencies =< 80 MHz

–

1 wait state for frequencies =< 60 MHz

●

Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)

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Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations

●

1-bit error correction, 2-bit error detection

1.5.6

On-chip SRAM with ECC

The SPC56XL60/54 SRAM provides a general-purpose single port memory.

ECC handling is done on a 32-bit boundary for data and it is extended to the address to

have the highest possible diagnostic coverage including the array internal address decoder.

SPC564L54L5 Datasheet(PDF) 14 Page - STMicroelectronics

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