SPC564L54L5 datasheet(127/160 Pages) STMICROELECTRONICS

127 / 160 page

SPC56XL60/54

Electrical characteristics

Doc ID 15457 Rev 8

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The reset sequences shown in Figure 16 and Figure 17 are triggered by functional reset

events. RESET is driven low during these two reset sequences only if the corresponding

functional reset source (which triggered the reset sequence) was enabled to drive RESET

low for the duration of the internal reset sequence(c).

3.19.3

Reset sequence trigger mapping

The following table shows the possible trigger events for the different reset sequences. It

specifies the reset sequence start conditions as well as the reset sequence end indications

that are the basis for the timing data provided in Table 32.

See RGM_FBRE register for more details.

Table 33.

Reset sequence trigger — reset sequence

Reset

Sequence

Trigger

Reset

Sequence

Start

Condition

Reset

Sequence

End

Indication

Reset Sequence

Destructiv

e Reset

Sequence,

BIST

enabled(1)

Destructiv

e Reset

Sequence,

BIST

disabled(1)

External

Reset

Sequenc

e Long,

BIST

enabled

Functiona

l Reset

Sequenc

e Long

Functiona

l Reset

Sequenc

e Short

All internal

destructive reset

sources

(LVDs or

internal HVD

during power-up

and during

operation)

Section ,

Destructive

reset

Release of

RESET(2)

triggers

cannot

trigger

cannot

trigger

cannot

trigger

Assertion of

RESET(3)

Section ,

External

reset via

RESET

cannot trigger

triggers(4)

triggers(5)

triggers(6)

All internal

functional reset

sources

configured for

long reset

Sequence

starts with

internal

reset

trigger

Release of

RESET(7)

cannot trigger

cannot

trigger

triggers

cannot

trigger

All internal

functional reset

sources

configured for

short reset

cannot trigger

cannot

trigger

cannot

trigger

triggers

Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.

End of the internal reset sequence (as specified in Table 32) can only be observed by release of RESET if it is not held low

externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till RESET is released

externally.

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