ST10F280_12 datasheet(155/239 Pages) STMICROELECTRONICS

155 / 239 page

ST10F280

CAN modules

Doc ID 8673 Rev. 3

155/239

CAN modules

The two integrated CAN modules (CAN1 and CAN2) are identical and handle the

completely autonomous transmission and reception of CAN frames in accordance with the

CAN specification V2.0 part B (active) i.e. the on-chip CAN module can receive and transmit

standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.

Because of duplication of CAN controllers, the following adjustements are to be considered:

●

The same internal register addresses both CAN controllers, but with the base

addresses differing in address bit A8 and separate chip select for each CAN module.

For address mapping, see Chapter 4.

●

The CAN1 transmit line (CAN1_TxD) is the alternate function of the port P4.6 and the

receive line (CAN1_RxD) is P4.5.

●

The CAN2 transmit line (CAN2_TxD) is the alternate function of the port P4.7 and the

receive line (CAN2_RxD) is the alternate function of the port P4.4.

●

Interrupt of CAN2 is connected to the XBUS interrupt line XP1 (CAN1 is on XP0).

●

Because of the new XPERCON register, both CAN modules have to be selected,

before the bit XPEN is set in SYSCON register.

●

After reset, the CAN1 is selected with the related control bit in the XPERCON register.

The CAN2 is not selected.

15.1

Memory mapping

15.1.1

CAN1

Address range 00’EF00h 00’EFFFh is reserved for the CAN1 Module access. The CAN1 is

enabled by setting bit 0 of the new XPERCON register before setting XPEN bit 2 of the

SYSCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit

data bus (byte accesses are possible). Two waitstates give an access time of 100 ns at

40MHz CPU clock. No tristate waitstate is used.

15.1.2

CAN2

Address range 00’EE00h 00’EEFFh is reserved for the CAN2 Module access. The CAN2 is

enabled by setting XPEN bit 2 of the SYSCON register and bit 1 of the new XPERCON

(byte accesses are possible). Two waitstates give an access time of 100 ns at 40MHz CPU

clock. No tristate waitstate is used.

Note:

If one or the two CAN modules are used, Port 4 can not be programmed to output all 8

segment address lines. Thus, only 4 segment address lines can be used, reducing the

external memory space to 5M Bytes (1M Byte per CS line).

15.2

CAN bus configurations

Depending on application, CAN bus configuration may be one single bus with a single or

multiple interfaces or a multiple bus with a single or multiple interfaces. The ST10F280 is

able to support these 2 cases.

ST10F280 Datasheet(PDF) 155 Page - STMicroelectronics

ST10F280 Datasheet(HTML) 155 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL