ST10F280_12 datasheet(180/239 Pages) STMICROELECTRONICS

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Power reduction modes

ST10F280

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Doc ID 8673 Rev. 3

Power reduction modes

Two different power reduction modes with different levels of power reduction have been

implemented in the ST10F280, which may be entered under software control.

In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode

can be terminated by any reset or interrupt request.

In Power Down mode both the CPU and the peripherals are stopped. Power Down mode

can now be configured by software in order to be terminated only by a hardware reset or by

a transition on enabled fast external interrupt pins.

Note:

All external bus actions are completed before Idle or Power Down mode is entered.

However, Idle or Power Down mode is not entered if READY is enabled, but has not been

activated (driven low for negative polarity, or driven high for positive polarity) during the last

bus access.

18.1

Idle mode

Idle mode is entered by running IDLE protected instruction. The CPU operation is stopped

and the peripherals still run.

Idle mode is terminate by any interrupt request. Whatever the interrupt is serviced or not,

the instruction following the IDLE instruction will be executed after return from interrupt

(RETI) instruction, then the CPU resumes the normal program.

Note that a PEC transfer keeps the CPU in Idle mode. If the PEC transfer does not succeed,

the Idle mode is terminated. Watchdog timer must be properly programmed to avoid any

disturbance during Idle mode.

18.2

Power down mode

Power Down mode starts by running PWRDN protected instruction. Internal clock is

stopped, all MCU parts are on hold including the watchdog timer.

There are two different operating Power Down modes: protected mode and interruptible

mode. The internal RAM contents can be preserved through the voltage supplied via the

VDD pins. To verify RAM integrity, some dedicated patterns may be written before entering

the Power Down mode and have to be checked after Power Down is resumed.

It is mandatory to keep VDD = +5V ±10% during power-down mode, because the on-chip

voltage regulator is turned in power saving mode and it delivers 2.5V to the core logic, but it

must be supplied at nominal VDD = +5V.

ST10F280 Datasheet(PDF) 180 Page - STMicroelectronics