ST10F280_12 datasheet(181/239 Pages) STMICROELECTRONICS

181 / 239 page

ST10F280

Power reduction modes

Doc ID 8673 Rev. 3

181/239

SYSCON

Address:

0xFF12H / 89h SFR

Reset:

0x0XX0h

Type:

R/W

Note:

18.2.1

Protected power down mode

This mode is selected by clearing the bit PWDCFG in register SYSCON to ‘0’.

In this mode, the Power Down mode can only be entered if the NMI (Non Maskable

Interrupt) pin is externally pulled low while the PWRDN instruction is executed.

This feature can be used in conjunction with an external power failure signal which pulls the

NMI pin low when a power failure is imminent. The microcontroller will enter the NMI trap

routine which can save the internal state into RAM. After the internal state has been saved,

the trap routine may set a flag or write a certain bit pattern into specific RAM locations, and

then execute the PWRDN instruction. If the NMI pin is still low at this time, Power Down

mode will be entered, otherwise program execution continues. During power down the

voltage delivered by the on-chip voltage regulator automatically lowers the internal logic

supply down to 2.5 V, saving the power while the contents of the internal RAM and all

registers will still be preserved.

Exiting power down mode

In this mode, the only way to exit Power Down mode is with an external hardware reset.

The initialization routine (executed upon reset) can check the identification flag or bit pattern

within RAM to determine whether the controller was initially switched on, or whether it was

properly restarted from Power Down mode.

18.2.2

Interruptable power down mode

This mode is selected by setting the bit PWDCFG in register SYSCON to ‘1’.

9876

5432

STKSZ

XPEN

R/W

PWDCFG Power Down Mode Configuration Control

0: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin

is low, otherwise the instruction has no effect. To exit Power Down Mode, an external reset

must occurs by asserting the RSTIN pin.

1: Power Down Mode can only be entered during PWRDN instruction execution if all

enabled FastExternal Interrupt (EXxIN) pins are in their inactive level. Exiting this mode

can be done by asserting one enabled EXxIN pin.

ST10F280 Datasheet(PDF) 181 Page - STMicroelectronics

ST10F280 Datasheet(HTML) 181 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL