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ST10F280 Datasheet(PDF) 217 Page - STMicroelectronics |
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ST10F280 Datasheet(HTML) 217 Page - STMicroelectronics |
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217 / 239 page ![]() ST10F280 Electrical characteristics Doc ID 8673 Rev. 3 217/239 t49 CC RdCS, WrCS Low Time (no R/W delay) 28 + tC – 3 TCL - 9.5 + tC –ns t50 CC Data valid to WrCS 10 + tC – 2 TCL - 15+ tC –ns t51 SR Data hold after RdCS 0– 0 – ns t52 SR Data float after RdCS (1) – 16.5 + tF – 2 TCL - 8.5+tF ns t54 CC Address hold after RdCS, WrCS 6 + tF – 2 TCL - 19 + tF –ns t56 CC Data hold after WrCS 6 + tF – 2 TCL - 19 + tF –ns 1. Partially tested, guaranteed by design characterization. Table 48. Multiplexed bus characteristics (continued) Symbol Parameter Max. CPU Clock = 40MHz Variable CPU Clock 1/2 TCL = 1 to 40MHz Min. Max. Min. Max. |
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