ST10F280_12 datasheet(213/239 Pages) STMICROELECTRONICS

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ST10F280

Electrical characteristics

Doc ID 8673 Rev. 3

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20.4.6

Oscillator Watchdog (OWD)

An on-chip watchdog oscillator is implemented in the ST10F280. This feature is used for

safety operation with external crystal oscillator (using direct drive mode with or without

prescaler). This watchdog oscillator operates as following:

The reset default configuration enables the watchdog oscillator. It can be disabled by setting

the OWDDIS (bit 4) of SYSCON register.

When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the

watchdog counter. The PLL free-running frequency is from 2 to 10MHz. On each transition

of external clock, the watchdog counter is cleared. If an external clock failure occurs, then

the watchdog counter overflows (after 16 PLL clock cycles).

The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator

watchdog Interrupt Request (XP3INT) is flagged. The CPU clock will not switch back to the

external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset can

switch the CPU clock source back to direct clock input.

When the OWD is disabled, the CPU clock is always external oscillator clock and the PLL is

switched off to decrease consumption supply current.

20.4.7

Phase locked loop

For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked

loop is enabled and it provides the CPU clock (see Table 45). The PLL multiplies the input

frequency by the factor F which is selected via the combination of pins P0.15-13 (fCPU =

fXTAL x F). With every F’th transition of fXTAL the PLL circuit synchronizes the CPU clock to

the input clock. This synchronization is done smoothly, so the CPU clock frequency does not

change abruptly.

Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is

locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of

individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated

using the minimum TCL that is possible under the respective circumstances.

The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to

keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to

one TCL period. It decreases according to the formula and to the Figure 74 given below. For

N periods of TCL the minimum value is computed using the corresponding deviation DN:

where N = number of consecutive TCL periods and 1

≤ N ≤ 40. So for a period of 3 TCL

periods (N = 3):

D3 = 4 - 3/15 = 3.8%

3TCLmin = 3 TCLNOM x (1 - 3.8/100) = 3 TCLNOM x 0.962

3TCLmin = (36.075ns at fCPU = 40MHz)

TCL

MIN

TCL

NOM

100

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–

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4N 15

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