ST10F280_12 datasheet(212/239 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F280

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Doc ID 8673 Rev. 3

20.4.4

Prescaler operation

When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the

internal oscillator (input clock signal) by a 2:1 prescaler.

The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e.

the duration of an individual TCL) is defined by the period of the input clock fXTAL.

The timings listed in the AC Characteristics that refer to TCL therefore can be calculated

using the period of fXTAL for any TCL.

Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running

frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,

then the PLL is switched off.

20.4.5

Direct drive

When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is

disabled and the CPU clock is directly driven from the internal oscillator with the input clock

signal.

The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL.

Therefor, the timings given in this chapter refer to the minimum TCL. This minimum value

can be calculated by the following formula:

For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated,

so the duration of 2 TCL is always 1/fXTAL.

The minimum value TCLmin has to be used only once for timings that require an odd number

of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:

Note:

The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of

TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin.

If the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running

frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,

then the PLL is switched off.

The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal

serial resistance of the crystal is less than 40

Ω. However, higher frequencies can be applied with an external clock source

on pin XTAL1, but in this case, the input clock signal must reach the defined levels VIL and VIH2..

TCL

min

⁄

ALl

xlDC

min

duty cycle

2TCL

1 f

XTAL

⁄

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