ST10F280_12 datasheet(208/239 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F280

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Doc ID 8673 Rev. 3

20.3.1

A/D converter characteristics

VDD = 5 V ± 10%, VSS = 0 V, TA = -40°C to 125°C, 4.0 V ≤ VAREF ≤ VDD + 0.1 V;

VSS0.1 V ≤ VAGND ≤ VSS + 0.2 V

Table 43.

A/D converter characteristics

Symbol

Parameter

Test

Condition

Min.

Max

Unit

VAREF

Analog Reference voltage

4.0

VDD + 0.1

VAIN

Analog input voltage

(1)(2)

VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result

in these cases will be X000h or X3FFh, respectively.

To remove noise and undesirable high frequency components from the analog input signal, a low-pass

filter must be connected at the ADC input. The cut-off frequency of this filter should avoid 2 opposite

transitions during the ts sampling time of the ST10 ADC:

- fcut-off ≤ 1 / 5 ts to 1/10 ts

where ts is the sampling time of the ST10 ADC and is not related to the Nyquist frequency determined by

the tc conversion time.

VAGND

VAREF

IAREF

Reference supply current

running mode

power-down mode

(3)

Partially tested, guaranteed by design characterization.

–

500

μA

CAIN

ADC input capacitance

Not sampling

Sampling

(3)

–

Sample time

(4)(5)

During the tS sample time the input capacitance Cain can be charged/discharged by the external source.

The internal resistance of the analog source must allow the capacitance to reach its final voltage level

within the tS sample time. After the end of the tS sample time, changes of the analog input voltage have no

effect on the conversion result. Values for the tSC sample clock depend on the programming. Referring to

the tC conversion time formula of section 20.3.2 and to the table 39 of page 156:

- tS min = 2 tSC min = 2 tCC min = 2 x 24 x TCL = 48 TCL

- tS max = 2 tSC max = 2 x 8 tCC max = 2 x 8 x 96 TCL = 1536 TCL

TCL is defined in section 20.4.5 at page 159.

This parameter is fixed by ADC control logic.

48 TCL

1 536 TCL

Conversion time

(6)(5)

The conversion time formula is:

- tC = 14 tCC + tS + 4 TCL (= 14 tCC + 2 tSC + 4 TCL)

The tC parameter includes the tS sample time, the time for determining the digital result and the time to load

the result register with the result of the conversion. Values for the tCC conversion clock depend on the

programming. Referring to the table 39 of page 156:

- tC min = 14 tCC min + tS min + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL

- tC max = 14 tCC max + tS max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL

388 TCL

2 884 TCL

DNL

Differential Nonlinearity

(7)

-0.5

+0.5

LSB

INL

Integral Nonlinearity

(7)

-1.5

+1.5

LSB

OFS

Offset Error

(7)

-1.0

+1.0

LSB

TUE

Total unadjusted error

(7)

-2.0

+2.0

LSB

RASRC SR

Internal resistance of analog

source

tS in [ns]

(4)(3)

–

(tS / 150) -

0.25

Coupling Factor between inputs

(8)(3)

–1/500

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