ST10F280_12 datasheet(233/239 Pages) STMICROELECTRONICS

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ST10F280

Electrical characteristics

Doc ID 8673 Rev. 3

233/239

Slave mode

VCC = 5 V ±10%, VSS = 0 V, CPU clock = 40 MHz, TA = -40°C to 125°C, CL = 50 pF

The formula for SSC Clock Cycle time is: t310 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned

16-bit integer.

Table 53.

SSC slave timing

Symbol

Parameter

Maximum Baud

rate=10MBd

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-

FFFFh)

Min.

Max.

Min.

Max.

t310

SR SSC clock cycle time

100

8 TCL

262144

TCL

t311

SR SSC clock high time

–

t310/2 - 10

–

t312

SR SSC clock low time

–

t310/2 - 10

–

t313

SR SSC clock rise time

–

t314

SR SSC clock fall time

–

t315

Write data valid after shift

edge

–39

–

2 TCL +

t316

Write data hold after shift

edge

0–

–

t317p

Read data setup time before

latch edge, phase error

detection on (SSCPEN = 1)

–

4 TCL +

–ns

t318p

(1)

Timing guaranteed by design.

Read data hold time after

latch edge, phase error

detection on (SSCPEN = 1)

–

6 TCL +

–ns

t317

Read data setup time before

latch edge, phase error

detection off (SSCPEN = 0)

6–

–

t318

Read data hold time after

latch edge, phase error

detection off (SSCPEN = 0)

–

2 TCL + 6

–

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