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ST10F280 Datasheet(PDF) 229 Page - STMicroelectronics |
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ST10F280 Datasheet(HTML) 229 Page - STMicroelectronics |
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229 / 239 page  ST10F280 Electrical characteristics Doc ID 8673 Rev. 3 229/239 Figure 88. CLKOUT and READY 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on R/W-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here. For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this delay is zero. 7. The next external bus cycle may start here. 20.4.13 External bus arbitration VDD = 5 V ± 10%, VSS = 0 V, TA = -40°C to 125°C, CL = 50 pF t30 t34 t35 t36 t35 t36 t58 t59 t58 t59 wait state READY MUX / Tri-state 6) t32 t33 t29 Running cycle 1) t31 t37 3) 3) 5) t60 4) 6) 2) 7) 3) 3) CLKOUT ALE RD, WR Synchronous Asynchronous READY READY GAPGCFT00942 Table 51. External bus arbitration Symbol Parameter Maximum CPU Clock = 40MHz Variable CPU Clock 1/2 TCL = 1 to 40MHz Min. Max. Min. Max. t61 SR HOLD input setup time to CLKOUT 15 – 15 – ns t62 CC CLKOUT to HLDA high or BREQ low delay – 12.5 – 12.5 ns t63 CC CLKOUT to HLDA low or BREQ high delay – 12.5 – 12.5 ns |
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