ST10F280_12 datasheet(228/239 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F280

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Doc ID 8673 Rev. 3

t34

CLKOUT rising edge to

ALE falling edge

-2 + tA

8 + tA

-2 + tA

8 + tA

t35

Synchronous READY

setup time to CLKOUT

12.5

–

12.5

–

t36

Synchronous READY hold

time after CLKOUT

2–

–

t37

Asynchronous READY low

time

–

2 TCL + 10

–

t58

Asynchronous READY

setup time (1)

12.5

–

12.5

–

t59

Asynchronous READY

hold time (1)

2–

–

t60

Asynchronous READY

hold time after RD, WR

high (Demultiplexed

Bus)(2)

0 + 2tA + tC +

(2)

TCL - 12.5

+ 2tA + tC + tF

(2)

These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

Demultiplexed bus is the worst case. For multiplexed bus 2 TCL are to be added to the maximum values.

This adds even more time for deactivating READY.

The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.

Table 50.

CLKOUT and READY characteristics (continued)

Symbol

Parameter

Maximum CPU Clock

= 40MHz

Variable CPU Clock

1/2 TCL = 1 to 40MHz

Min.

Max.

Min.

Max.

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