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ST10F280 Datasheet(PDF) 227 Page - STMicroelectronics |
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ST10F280 Datasheet(HTML) 227 Page - STMicroelectronics |
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227 / 239 page  ST10F280 Electrical characteristics Doc ID 8673 Rev. 3 227/239 Figure 87. External memory cycle: demultiplexed bus, no read / write delay, extended ALE, read /write chip select 20.4.12 CLKOUT and READY VDD = 5 V ± 10%, VSS = 0 V, TA = -40°C to 125°C, CL = 50 pF Address t 5 t 16 t 46 t 57 t 6 t 53 t 26 t 17 t 47 t 48 t 49 t 48 t 49 t 50 Data In t 51 t 68 t 55 Data Out t 82 t 83 t 82 t 83 Read Cycle Write Cycle CLKOUT ALE RdCSx WrCSx Data Bus (P0) (D15-D8) D7-D0 Data Bus (P0) (D15-D8) D7-D0 A23-A16 A15-A0 (P1) BHE GAPGCFT00941 Table 50. CLKOUT and READY characteristics Symbol Parameter Maximum CPU Clock = 40MHz Variable CPU Clock 1/2 TCL = 1 to 40MHz Min. Max. Min. Max. t29 CC CLKOUT cycle time 25 25 2 TCL 2TCL ns t30 CC CLKOUT high time 4 – TCL – 8.5 – ns t31 CC CLKOUT low time 3 – TCL – 9.5 – ns t32 CC CLKOUT rise time – 4 – 4 ns t33 CC CLKOUT fall time – 4 – 4 ns |
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