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CXP87452 Datasheet(PDF) 12 Page - Sony Corporation |
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CXP87452 Datasheet(HTML) 12 Page - Sony Corporation |
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12 / 32 page  – 12 – CXP87452/87460 IP Schmitt input To SIO SO0 output enable SO0 from SIO IP Schmitt input Pull-up resistor From power on reset circuit (mask option) Mask option OP IP CPU mode IP OSCI OSCO Fig. 1 IP Fig. 2 Data bus PI0/PCK or PK0 Note) Circuit format of Fig. 1 or Fig. 2 can be selected with mask option. RD Port I Port K CS0 SI0 2 pins Hi-Z SO0 2 pins RST 1 pin L level MP 1 pin Hi-Z Port I Port K Oscillation Hi-Z PI0/PCK/OSCI PK0/OSCO 2 pins SCK0 output enable Internal serial clock from SIO IP Schmitt input External serial clock to SIO IP EXTAL XTAL • Shows the circuit composition during oscillation. • Feedback resistor is removed during stop. 1 pin Hi-Z SCK0 1 pin Hi-Z EXTAL XTAL Oscillation Pin When reset Circuit format |
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