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CXP87452 Datasheet(PDF) 27 Page - Sony Corporation |
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CXP87452 Datasheet(HTML) 27 Page - Sony Corporation |
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27 / 32 page ![]() – 27 – CXP87452/87460 (7) Others (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V) Item CFG input high and low level widths DFG input high and low level widths DPG minimum pulse width DPG minimum removal time PBCTL input high and low level widths EXI input high and low level widths PMI input high and low level widths PMSK input high and low level widths tCFH tCFL tDFH tDFL tDPW trem tCTH tCTL tEIH tEIL tPIH tPIL tPSH tPSL CFG DFG DPG DPG PBCTL EXI0 EXI1 PMI PMSK ns ns ns ns ns ns ns ns Symbol Pin Min. tFRC × 24 + 200 tFRC × 8 + 200 50 50 tFRC × 8 + tsys + 200 tFRC × 8 + tsys + 200 tsys + 200 tsys + 200 Max. Unit tsys = 2000/fc tsys = 2000/fc Condition Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The value of tFRC is as follows by selecting FRC clock (FRCS: 01EEH bit 7) When PS0 is selected, tFRC = 1000/fc (ns) When PS1 is selected, tFRC = 2000/fc (ns) |
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