WM8850 datasheet(22/223 Pages) WOLFSON

22 / 223 page

WM8850

Pre-Production

PP, April 2011, Rev 3.2

Test Conditions

AVDD = CPVDD = 5V, DBVDD = 3.3V, DCVDD = 1.8V, TA = +25

oC, 1kHz signal, fs = 48kHz, 24-bit data unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

S/PDIF Receiver Specification

Input Signal Level

IEC-60958 Compatible Input Mode

200

500

mVp-p

Input Signal Logic High

VIH(S/PDIF)

Normal CMOS Compatible Input Mode

0.7 *

DBVDD

Low-Amplitude CMOS Compatible Input Mode

0.4 *

DBVDD

1.8

Input Signal Logic Low

VIL(S/PDIF)

Normal CMOS Compatible Input Mode

0.3 *

DBVDD

Low-Amplitude CMOS Compatible Input Mode

DBVDD

x 0.2

Input Pin Bias Voltage

IEC-60958 Compatible Input Mode

0.5 *

DCVDD

Input Impedance

ZIN

IEC-60958 Compatible Input Mode

7.5

kΩ

Normal CMOS Compatible Input Mode

100

kΩ

Input Hysteresis

IEC-60958 Compatible Input Mode

Normal CMOS Compatible Input Mode

300

Low-Amplitude CMOS Compatible Input Mode

150

Input Sample Rate Lock

Tolerance

Includes maximum reference clock error of

±0.025% as allowed by HDA Specification

10000

ppm

-1

Lock Delay

192

Frame

Blocks

S/PDIF Stream Jitter

Tolerance

UI = 1/fs(in)

Input Sample Rate

Support

44.1

88.2

kHz

WM8850 Datasheet(PDF) 22 Page - Wolfson Microelectronics plc

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