WM9093ECSSLASHR datasheet(31/84 Pages) WOLFSON

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Production Data

WM9093

PD, March 2012, Rev 4.2

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

AGC_CLIP_DCY [2:0]

000

AGC Anti-Clip Decay Rate

Sets the rate of AGC gain

increments after a period of clipping

000 = 120ms/6dB

001 = 480ms/6dB

010 = 820ms/6dB

011 = 1170ms/6dB

100 = 1640ms/6dB

101 = 2050ms/6dB

110 = 2730ms/6dB

111 = 4100ms/6dB

Table 13 AGC Anti-Clip Control

AGC POWER LIMITING

The second mechanism used by the AGC to monitor signal conditions is the power limit function. The

speaker output voltage is measured, and the corresponding power output is determined. The power

limiting function can be disabled using the AGC_PWR_ENA bit. It is enabled by default.

The power output threshold at which the AGC will apply attenuation is set using the AGC_PWR_THR

power levels, assuming an 8

 speaker.

The power output threshold is also controlled by the AGC_PWR_AVG register. When

AGC_PWR_AVG = 1, then the AGC responds to the RMS power level as quoted above. When

AGC_PWR_AVG = 0, then the AGC responds to the instantaneous voltage at the speaker output.

Selecting the RMS power level is recommended, as this represents the average signal level.

When the AGC applies signal attenuation triggered by the power limit threshold, the signal gain is

reduced at a rate that is set by the AGC_PWR_ATK register. When the power limit threshold is no

longer met (due to the signal level reduction), then the AGC increases the signal gain at a rate set by

the AGC_PWR_DCY register.

Note that, when the anti-clip and power limiting thresholds are both triggered concurrently, then the

signal gain is reduced at the rate set by the AGC_CLIP_ATK register and is increased at the rate set

by AGC_PWR_DCY. These fields are defined in Table 13 and Table 14 respectively.

WM9093ECS/R Datasheet(PDF) 31 Page - Wolfson Microelectronics plc