AOZ1081AI datasheet(11/16 Pages) AOSMD

11 / 16 page

AOZ1081

Rev. 1.1 April 2009

www.aosmd.com

Page 11 of 16

Loop Compensation

The AOZ1081 employs peak current mode control for

easy use and fast transient response. Peak current mode

control eliminates the double pole effect of the output

L&C filter. It greatly simplifies the compensation loop

design.

With peak current mode control, the buck power stage

can be simplified to be a one-pole and one-zero system

in frequency domain. The pole is dominant pole and can

be calculated by:

The zero is a ESR zero due to output capacitor and its

ESR. It is can be calculated by:

where;

CO is the output filter capacitor,

RL is load resistor value, and

ESRCO is the equivalent series resistance of output capacitor.

The compensation design is actually to shape the

converter close loop transfer function to get desired gain

and phase. Several different types of compensation

network can be used for AOZ1081. For most cases, a

series capacitor and resistor network connected to the

COMP pin sets the pole-zero and is adequate for a stable

high-bandwidth control loop.

In the AOZ1081, FB pin and COMP pin are the inverting

input and the output of internal transconductance error

amplifier. A series R and C compensation network con-

nected to COMP provides one pole and one zero. The

pole is:

where;

GEA is the error amplifier transconductance, which is 200 x 10-6

A/V,

GVEA is the error amplifier voltage gain, which is 500 V/V, and

CC is compensation capacitor.

The zero given by the external compensation network,

capacitor CC (C5 in Figure 1) and resistor RC (R1 in

Figure 1), is located at:

To design the compensation circuit, a target crossover

frequency fC for close loop must be selected. The system

crossover frequency is where control loop has unity gain.

The crossover frequency is also called the converter

bandwidth. Generally a higher bandwidth means faster

response to load transient. However, the bandwidth

should not be too high due to system stability concern.

When designing the compensation loop, converter

stability under all line and load condition must be

considered.

Usually, it is recommended to set the bandwidth to be

less than 1/10 of switching frequency. The AOZ1081

operates at a fixed switching frequency range from

750kHz to 1.15MHz. It is recommended to choose a

crossover frequency less than 75kHz.

The strategy for choosing RC and CC is to set the cross

over frequency with RC and set the compensator zero

with CC. Using selected crossover frequency, fC, to

calculate RC:

where;

fC is desired crossover frequency,

VFB is 0.25V,

GEA is the error amplifier transconductance, which is 200x10-6

A/V, and

GCS is the current sense circuit transconductance, which is

5.64 A/V.

The compensation capacitor CC and resistor RC together

make a zero. This zero is put somewhere close to the

dominate pole fp1 but lower than 1/5 of selected

crossover frequency. CC can is selected byy:

The equation above can also be simplified to:

fp1

π CO RL

-----------------------------------

fZ1

π CO ESRCO

------------------------------------------------

fp2

GEA

π CC GVEA

-------------------------------------------

fZ2

π CC RC

-----------------------------------

75kHz

VFB

----------

π CO

GEA GCS

------------------------------

1.5

π RC fp1

-----------------------------------

CO RL

---------------------

AOZ1081AI Datasheet(PDF) 11 Page - Alpha & Omega Semiconductors

AOZ1081AI Datasheet(HTML) 11 Page - Alpha & Omega Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Download

Link URL