AOZ1081AI datasheet(12/16 Pages) AOSMD

12 / 16 page

AOZ1081

Rev. 1.1 April 2009

www.aosmd.com

Page 12 of 16

Thermal Management and Layout Consideration

In the AOZ1081 buck regulator circuit, high pulsing

current flows through two circuit loops. The first loop

starts from the input capacitors, to the VIN pin, to the

LX pins, to the filter inductor, to the output capacitor and

load, and then return to the input capacitor through

ground. Current flows in the first loop when the high side

switch is on. The second loop starts from inductor, to the

output capacitors and load, to the PGND pin of the

AOZ1081, to the LX pins of the AZO1081. Current flows

in the second loop when the low side diode is on.

In PCB layout, minimizing the two loops area reduces the

noise of this circuit and improves efficiency. A ground

plane is recommended to connect input capacitor, output

capacitor, and PGND pin of the AOZ1081.

In the AOZ1081 buck regulator circuit, the two major

power dissipating components are the AOZ1081 and

output inductor. The total power dissipation of converter

circuit can be measured by input power minus output

power.

The power dissipation of inductor can be approximately

calculated by output current and DCR of inductor.

The actual AOZ1081 junction temperature can be calcu-

lated with power dissipation in the AOZ1081 and thermal

impedance from junction to ambient.

The maximum junction temperature of AOZ1081 is

150°C, which limits the maximum load current capability.

Please see the thermal de-rating curves for the maximum

load current of the AOZ1081 under different ambient

temperature.

The thermal performance of the AOZ1081 is strongly

affected by the PCB layout. Extra care should be taken

by users during design process to ensure that the IC will

operate under the recommended environmental

conditions.

Several layout tips are listed below for the best electric

and thermal performance. Figure 3 on the next page

illustrates a single layer PCB layout example as refer-

ence.

1. Do not use thermal relief connection to the VIN and

the PGND pin. Pour a maximized copper area to

the PGND pin and the VIN pin to help thermal

dissipation.

2. Input capacitor should be connected to the VIN pin

and the PGND pin as close as possible.

3. A ground plane is preferred. If a ground plane is not

used, separate PGND from AGND and connect

them only at one point to avoid the PGND pin noise

coupling to the AGND pin. In this case, a decoupling

capacitor should be connected between VIN pin and

AGND pin.

4. Make the current trace from LX pins to L to Co to the

PGND as short as possible.

5. Pour copper plane on all unused board area and

connect it to stable DC nodes, like VIN, GND or

VOUT.

6. The two LX pins are connected to internal PFET

drain. They are low resistance thermal conduction

path and most noisy switching node. Connected a

copper plane to LX pin to help thermal dissipation.

This copper plane should not be too larger otherwise

switching noise may be coupled to other part of

circuit.

7. Keep sensitive signal trace such as trace connected

with FB pin and COMP pin far away form the LX pins.

Ptotal_loss

VIN IIN VO IO

–

Pinductor_loss IO 2 Rinductor 1.1

Tjunction

Ptotal_loss Pinductor_loss

–

() Θ Tambient

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