ACT5260 datasheet(4/10 Pages) AEROFLEX

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SCD5260PC REV A 9/15/97 Plainview NY (516) 694-6700

Boot Time Mode Stream Comparison Chart – 5260 vs 4700

5260

4700

Mode Bit

Description

Mode Bit

Description

Reserved (must be zero)

Reserved: Must be zero (0)

4..1

Write-back data rate

→ DDDD

1 → DDxDDx

2 → DDxxDDxx

3 → DxDxDxDx

4 → DDxxxDDxxx

5 → DDxxxxDDxxxx

6 → DxxDxxDxxDxx

7 → DDxxxxxxDDxxxxxx

8 → DxxxDxxxDxxxDxxx

9−15 reserved

4..1

Write-back data rate

→ D

1 → DDx

2 → DDxx

3 → DxDx

4 → DDxxx

5 → DDxxxx

6 → DxxDxx

7 → DDxxxxxx

8 → DxxxDxxx

9−15 reserved

7..5

Pclock to SysClock Multiplier

→ Multiply by 2, 1 → Multiply by 3

→ Multiply by 4, 3 → Multiply by 5

→ Multiply by 6, 5 → Multiply by 7

→ Multiply by 8, 7 reserved

7..5

Clock divisor

→ 2,1 → 3

→ 4, 3 → 5

→ 6, 5 → 7

→ 8, 7 → reserved

Specifies byte ordering. Logically ORed with

BigEndian input signal.

→ Little endian

→ Big endian

→ Little endian

→ Big endian

10..9

→ R4000 compatible non-block writes,

→ reserved,

→ pipelined non-block writes,

→ non-block write re-issue

10..9

→ R4000 compatible,

→ reserved,

→ pipelined writes,

→ write re-issue

→ Enable the timer interrupt on Int[5],

→ Disable the timer interrupt on Int[5].

→ Enable the timer interrupt on Int[5],

→ Disable the timer interrupt on Int[5].

Reserved: Must be zero (0)

14..13

Output driver strength

→ 100% strength (fastest), 11 → 83%

strength, 00

→ 67% strength, 01 → 50%

strength (slowest)

14..13

Output driver strength

→ 100% strength (fastest), 11 → 83%

strength, 00

→ 67% strength, 01 → 50%

strength (slowest)

Reserved: Must be zero (0)

⇒ TClock[0] enabled,

⇒ TClock[0] disabled

17..16

System configuration identifiers - software

visible in processor Config[21..20]

⇒ TClock[1] enabled,

⇒ TClock[1] disabled

⇒ RClock[0] enabled,

⇒ RClock[0] disabled

→ Set Timer/Counter to run at Pclock/2

→ Set Timer/Counter to run at Pclock

⇒ RClock[1] enabled,

⇒ RClock[1] disabled

21..19

Reserved: Must be zero (0)

255..19

Reserved: Must be zero (0)

24..22

Write address to write data delay in P cycles

000

→ 0 cycles(R5000), ..., 111 → 7 cycles

255..25

Reserved: Must be zero (0)

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