WM8783

Production Data

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PD, August 2010, Rev 4.0

10

DEVICE DESCRIPTION

INTRODUCTION

The WM8783 is a low-cost ADC designed for set-top boxes and DVD applications. It is packaged in

an 8-pin SOIC.

The device comprises two analogue input pins, each accepting line signals up to 1Vrms. The signal

path gain is fixed.

The stereo hi-fi ADCs operate at sample rates from 8kHz up to 96kHz. A high pass filter is provided

in the ADC path for removing DC offsets and suppressing low frequency noise.

The digital audio interface supports the ADC output in stereo 24-bit I2S format. The device requires

no configuration instructions and automatically selects the ADC sample rate according to the external

master clock (MCLK) frequency.

The WM8783 incorporates an internal voltage reference and LDO regulator for power-efficient

operation from a single AVDD power supply. External clocking is required via the MCLK and LRCLK

pins.

A power on reset circuit ensures correct start-up and shut-down when AVDD is switched on or off.

The WM8783 is held in reset when MCLK not present, offering a low-power standby state.

ANALOGUE-TO-DIGITAL CONVERTER (ADC)

The WM8783 has two analogue input pins, INL and INR. The maximum analogue input signal level

varies with AVDD, but is typically 0dBV (1Vrms) when AVDD = 3.3V. This is suitable for single-ended

connection to line level input signals.

The WM8783 uses two 24-bit sigma-delta ADCs. The use of multi-bit feedback and high

oversampling rates reduces the effects of jitter and high frequency noise. The sample rate is set

automatically according to the external clocks connected to LRCLK and MCLK. Many common

sample rates from 8kHz to 96kHz are supported, as described in the “Digital Audio Interface” section.

Digital filters are also incorporated on the ADC output signal path to remove DC offsets and other

unwanted noise. The cut-off frequency of the ADC high-pass filter varies with the ADC sample rate

(fs), but is typically 4Hz when fs = 48kHz.

Filter response plots for the ADC high-pass filter are shown in “Digital Filter Characteristics”.

DIGITAL AUDIO INTERFACE

The digital audio interface is used for outputting ADC data from the WM8783. It uses three pins:



ADCDAT - ADC data output



LRCLK - Left / Right data alignment clock



MCLK - Master clock

The WM8783 operates as a Slave device only; LRCLK and MCLK must be provided as inputs.

It is a requirement of the WM8783 digital audio interface that the bit rate of the ADCDAT data is 64fs

only, where fs is the audio sample rate.

Note that the Bit Clock (BCLK) associated with the digital audio interface is configured and generated

automatically within the WM8783. This allows the ADCDAT to be synchronised to the BCLK in the

host processor, even though the BCLK is not connected externally to the WM8783.