WM8903CLGEFKSLASHR datasheet(95/178 Pages) WOLFSON

95 / 178 page

Production Data

WM8903

PD, Rev 4.5, June 2012

Note: When the digital sidetone is enabled, ADC data will continue to be added to DAC data when

loopback is enabled.

CLOCKING AND SAMPLE RATES

The WM8903 supports a wide range of standard audio sample rates from 8kHz to 96kHz. When the

DAC and ADC are both enabled, they operate at the same sample rate, fs. Oversample rates of 64fs

or 128fs are supported (based on a 48kHz sample rate).

Note that simultaneous ADC and DAC operation at 88.2kHz or 96kHz is not possible. Digital

microphone operation is not supported at 88.2kHz or 96kHz sample rates. The clocking options for

88.2kHz or 96kHz ADC operation are restricted to specific configurations only, as detailed in this

section.

The internal clocks for the WM8903 are all derived from a common internal clock source, CLK_SYS.

This clock is the reference for the ADCs, DACs, DSP core functions, digital audio interface, DC servo

control and other internal functions.

CLK_SYS can either be derived directly from MCLK, or may be generated from a Frequency Locked

Loop (FLL) using MCLK, BCLK or LRC as a reference. Many commonly-used audio sample rates can

be derived directly from typical MCLK frequencies; the FLL provides additional flexibility for a wide

range of MCLK frequencies. To avoid audible glitches, all clock configurations must be set up before

enabling playback. The FLL can be used to generate a free-running clock in the absence of an

external reference source; see “Frequency Locked Loop (FLL)” for further details.

The WM8903 supports automatic clocking configuration. The programmable dividers associated with

the ADCs, DACs, DSP core functions and DC servo are configured automatically, with values

determined from the SAMPLE_RATE, CLK_SYS_RATE and CLK_SYS_MODE fields. Note that the

user must also configure the Digital Audio Interface.

A 256kHz clock, supporting the Control Write Sequencer, MICBIAS Current Detect filtering and a

number of internal functions, is derived from CLK_SYS. This clock is enabled by WSMD_CLK_ENA.

A slow clock, TOCLK, is used to de-bounce the button/accessory detect inputs, and to set the timeout

period for volume updates when zero-cross detect is used. This clock is enabled by TO_ENA.

The Charge Pump and DC servo control functions are clocked from CLK_SYS.

In master mode, BCLK is derived from CLK_SYS via a programmable divider set by BCLK_DIV. In

master mode, the LRC is derived from BCLK via a programmable divider LRCLK_RATE. The LRC

can be derived from an internal or external BCLK source, allowing mixed master/slave operation.

The overall clocking scheme for the WM8903 is illustrated in Figure 55. Note that BCLK and LRC are

described in the “Digital Audio Interface” section.

WM8903CLGEFK/R Datasheet(PDF) 95 Page - Wolfson Microelectronics plc