SPC5604SF2VLQ6 datasheet(2/136 Pages) FREESCALE

2 / 136 page

MPC5606S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

mode), and UART support; compliant with LIN protocol

rev 2.1

• 2 full CAN 2.0B controllers with 64 configurable buffers

each; bit rate programmable up to 1 Mbit/s

• Up to 4 Inter-integrated circuit (I2C) internal bus

controllers with master/slave bus interface

• Up to 133 configurable general purpose pins supporting

input and output operations

• Real Time Counter (RTC) with multiple clock sources:

– 128 kHz slow internal RC oscillator or 16 MHz fast

internal RC oscillator supporting autonomous wakeup

with 1 ms resolution with maximum timeout of 2

seconds

– 32 kHz slow external crystal oscillator, supporting

wakeup with 1 s resolution and maximum timeout of

one hour

– 4–16 MHz fast external crystal oscillator

• System timers:

– 4-channel 32-bit System Timer Module

(STM)—included in processor platform

– 4-channel 32-bit Periodic Interrupt Timer (PIT) module

– Software Watchdog Timer (SWT)

• System Integration Unit (SIU) module to manage resets,

external interrupts, GPIO, and pad control

• System Status and Configuration Module (SSCM) to

provide information for identification of the device, last

boot mode, or debug status, and provides an entry point for

the censorship password mechanism

• Clock Generation Module (MC_CGM) to generate system

clock sources and provide a unified register interface,

enabling access to all clock sources

• Clock Monitor Unit (CMU) to monitor the integrity of the

main crystal oscillator and the PLL and act as a frequency

meter, measuring the frequency of one clock source and

comparing it to a reference clock

• Mode Entry Module (MC_ME) to control the device

power mode, in other words, Run, Halt, Stop, or Standby

control mode transition sequences, and manage the power

control, voltage regulator, clock generation, and clock

management modules

• Reset Generation Module (MC_RGM) to manage reset

assertion and release to the device at initial startup

• Nexus development interface (NDI) per IEEE-ISTO

5001-2003 Class Two Plus standard

• Device/board boundary-scan testing supported per Joint

Test Action Group (JTAG) of IEEE (IEEE 1149.1)

• On-chip voltage regulator controller for regulating the 3.3

or 5 V supply voltage down to 1.2 V for core logic

(requires external ballast transistor)

• The MPC5606S microcontrollers are offered in the

following packages:1

– 144 LQFP, 0.5 mm pitch, 20 mm

 20 mm outline

– 176 LQFP, 0.5 mm pitch, 24 mm

 24 mm outline

– 208 MAPBGA, 1.0 mm pitch, 17 mm

 17 mm outline

(not a production package; available in limited

quantities for tool development only)

1. See the device comparison table or orderable parts

summary for package offerings for each device in the family.

SPC5604SF2VLQ6 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc

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