ST1S40IPUR datasheet(11/30 Pages) STMICROELECTRONICS

11 / 30 page

ST1S40

Functional description

Doc ID 17928 Rev 4

11/30

Equation 9

Equation 10

whereas the zero is defined as:

Equation 11

The embedded compensation network is RC=70 kΩ, CC=195 pF while CP and CO can be

considered as negligible. The error amplifier output resistance is 240 M

Ω so the relevant

singularities are:

Equation 12

so by closing the loop, the loop gain GLOOP(s) is:

Equation 13

Example:

VIN=12 V, VOUT=1.2 V, Iomax=3 A, L=1.5 µH, Cout=47 µF (MLCC), R1=10 k

Ω,

R2=20 k

Ω (see Section 6.2 and Section 6.3 for inductor and output capacitor selection

guidelines).

The module and phase Bode plot are reported in Figure 6.

The bandwidth is 100 kHz and the phase margin is 45 degrees.

P LF

π R

⋅⋅

⋅

----------------------------------

P HF

π R

()

⋅⋅

⋅

----------------------------------------------------

π R

⋅⋅

⋅

---------------------------------

11 6 kHz

P LF

34 Hz

LOOP s

()

CO s

() G

DIV s

() G

EA s

()

⋅⋅

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