ST1S40IPUR datasheet(18/30 Pages) STMICROELECTRONICS

18 / 30 page

Application information

ST1S40

18/30

Doc ID 17928 Rev 4

where IQ is the quiescent current (IQ=2.5 mA maximum).

The junction temperature TJ can be calculated as:

Equation 25

where TA is the ambient temperature and PTOT is the sum of the power losses just seen.

RthJA is the equivalent thermal resistance junction to ambient of the device; it can be

calculated as the parallel of many paths of heat conduction from the junction to the ambient.

For this device the path through the exposed pad is the one conducting the largest amount

of heat. The RthJA measured on the demonstration board described in the following

paragraph is about 40 °C/W for the VFQFPN and HSOP packages and about 55 °C/W for

the SO8-BW package.

Figure 7.

Switching losses

6.5

Layout consideration

The PC board layout of switching DC-DC regulator is very important in order to minimize the

noise injected in high impedance nodes, to reduce interferences generated by the high

switching current loops, and to optimize the reliability of the device.

In order to avoid EMC problems, the high switching current loops must be as short as

possible. In the buck converter there are two high switching current loops: during the ON

time, the pulsed current flows through the input capacitor, the high side power switch, the

inductor and the output capacitor; during the OFF time, through the low side power switch,

the inductor and the output capacitor.

The input capacitor connected to VINSW must be placed as close as possible to the device,

to avoid spikes on VINSW due to the stray inductance and the pulsed input current.

Rth

TOT

⋅

VSW

ISW,HS

VIN

VDS,HS

PCOND,HS

PCOND,LS

PSW

TFALL

TRISE

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