M68ICS08GR datasheet(263/408 Pages) FREESCALE

263 / 408 page

Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Communications Interface (SCI)

263

Figure 18-13. Flag Clearing Sequence

PE — Receiver Parity Error Bit

This clearable, read-only bit is set when the SCI detects a parity error

in incoming data. PE generates a PE CPU interrupt request if the

PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with

PE set and then reading the SCDR. Reset clears the PE bit.

1 = Parity error detected

0 = No parity error detected

BYTE 1

NORMAL FLAG CLEARING SEQUENCE

READ SCS1

SCRF = 1

READ SCDR

BYTE 1

BYTE 2

BYTE 3

BYTE 4

OR = 0

READ SCS1

SCRF = 1

OR = 0

READ SCDR

BYTE 2

READ SCS1

SCRF = 1

OR = 0

READ SCDR

BYTE 3

BYTE 1

READ SCS1

SCRF = 1

READ SCDR

BYTE 1

BYTE 2

BYTE 3

BYTE 4

OR = 0

READ SCS1

SCRF = 1

OR = 1

READ SCDR

BYTE 3

DELAYED FLAG CLEARING SEQUENCE

Freescale Semiconductor, Inc.

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